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rev. 1.00 1 october 20, 2015 rev. 1.00 pb october 26, 2015 BC9824 low power high performance 2.4ghz gfsk transceiver features ? 2400-2483.5m hz ism band operation ? support 250kbps,1mbps and 2mbps air data rate ? programmable output power ? low power consumption ? tolerate 60ppm 16mhz crystal ? variable payload length from 1 to 32bytes ? automatic packet processing ? 6 data pipes for 1:6 star networks ? 1.9v to 3.6v power supply ? 4-pin spi interface with maximum 8mhz clock rate ? 20-pin qfn package applications ? wireless pc peripherals ? wireless mice and keyboards ? wireless gamepads ? wireless audio ? voip and wireless headsets ? remote controls ? consumer electronics ? home automation ? toys ? personal health and entertainment general description BC9824 is a gfsk transceiver operating in the world wide ism frequency band at 2400 ~2483.5 m hz. burst mode transmission and up to 2mbps air data rate make them s uitable for applications requiring ultra low power consumption. the embedded packet processing engines enable their full operation with a very simple mcu as a radio system. auto re-transmission and auto acknowledge give reliable link without any mcu interference. BC9824 operates in tdd mode, either as a transmitter or as a receiver. the rf channel frequency determines the center of the channel used by BC9824 . the frequency is set by the r f_ch r egister i n r egister b ank 0 a ccording t o t he following form ula : f0= 2400 + rf_ch ( mhz ) . t he resolution of the rf channel frequency is 1mhz. a transmitter and a receiver must be programmed with the same rf channel frequency to be able to communicate with each other. the output power of BC9824 is set by the rf_pwr bits in the rf_setup register. demodulation is done with embedded data slicer and bit recovery logic. the air data rate can be programmed to 250kbps, 1mbps or 2mbps by rf_dr _high and rf_dr_low register . a transmitter and a receiver must be programmed with the same setting. in the following c hapters, a ll re gisters a re i n re gister bank 0 except with explicit claim. block diagram integrated tdd rf transceiver xtaln xtalp fm demodulator fm modulator data slicer rx fifo tx fifo gaussian shaping packet processing & state control spi interface power management ce irq csn sck mosi miso rfp rfn register banks
rev. 1.00 2 october 20, 2015 BC9824 pin assignment mosi BC9824 20 qfn-a vss vddpa rfp rfn vss vdd3rxrf sck vss xtalp xtaln csn irq miso ce nc vss vdd3b cdvdd vdd3if 1 2 3 4 5 678910 11 12 13 14 15 161718 19 20 pin description pin no. symbol i/o function description rf and analog 2 rfp rf rf output (pa)/input (lna), port p 3 rfn rf rf output (pa)/input (lna), port n 7 cdvdd o digital regulator output decoupling capacitor 18 xtalp o crystal oscillator, node p (inverter output) 19 xtaln i crystal oscillator, node n (inverter input) digital 11 ce di chip enable activates rx or tx mode 12 csn di spi chip select, active low 13 irq do maskable interrupt pin, active low 14 miso do spi slave data output with tri-state option 15 mosi di spi slave data input 16 sck di spi clock power and ground 1 vddpa power 1.8v regulator output for pa,tx:1.8v, rx:0v 5 vdd3rxrf power rx front-end power supply (1.9v to 3.6v dc) 6 vdd3if power rx/tx if power supply (1.9v to 3.6v dc) 8 vdd3b power digital power supply (1.9v to 3.6v dc) 4 vss ground ground (0v) 9 vss ground ground (0v) 17 vss ground ground (0v) 20 vss ground ground (0v) 10 nc ? no connection
rev. 1.00 3 october 20, 2015 BC9824 electrical characteristics name parameter (condition) min typical max unit comment operating condition v dd voltage 1.9 3.0 3.6 v temp temperature -20 +27 +85 oc digital input pin v ih high level 0.7v dd 5.25 v v il low level v ss 0.3v dd v digital output pin v oh high level (i oh =-0.25ma) v dd - 0.3 v dd v v ol low level(i ol =0.25ma) 0 0.3 v normal condition i vdd power down current 4 ua i vdd standby-i current 90 ua i vdd standby-ii current 330 ua normal rf condition f op operating frequency 2400 2527 mhz f xtal crystal frequency 16 mhz r fsk air data rate 250 2000 kbps transmitter p rf output power -40 0 3 dbm p bw modulation 20 db bandwidth(2mbps) 2.5 mhz p bw modulation 20 db bandwidth (1mbps) 1.8 mhz p bw modulation 20 db bandwidth ( 250kbps) 1.6 mhz i vdd current at -35 dbm output power 8 ma i vdd current at -25 dbm output power 9 ma i vdd current at -20 dbm output power 10 ma i vdd current at -10 dbm output power 12 ma i vdd current at -6 dbm output power 13 ma i vdd current at -1dbm output power 18 ma i vdd current at 3 dbm output power 25 ma receiver i vdd current (2mbps) 18 ma rx no signal i vdd current (1mbps) 18 ma rx no signal i vdd current (250kbps) 18 ma rx no signal max input 1 e-3 ber 20 dbm rx sens 1 e-3 ber sensitivity (2mbps) -87 dbm rx sens 1 e-3 ber sensitivity (1mbps) -90 dbm rx sens 1 e-3 ber sensitivity (250kbps) -96 dbm c/i co co-channel c/i (2mbps) 6 db c/i +1st acs c/i 2mhz (2mbps) 2 db c/i -1st acs c/i 2mhz (2mbps) -6 db c/i +2nd acs c/i 4mhz (2mbps) -21 db c/i -2nd acs c/i 4mhz (2mbps) -12 db c/i +3rd acs c/i 6mhz (2mbps) -29 db c/i -3rd acs c/i 6mhz (2mbps) -18 db c/i co co-channel c/i (1mbps) 6 db c/i +1st acs c/i 1mhz (1mbps) 4 db c/i -1st acs c/i 1mhz (1mbps) -6 db
rev. 1.00 4 october 20, 2015 BC9824 name parameter (condition) min typical max unit comment c/i +2nd acs c/i 2mhz (1mbps) -24 db c/i -2nd acs c/i 2mhz (1mbps) -12 db c/i +3rd acs c/i 3mhz (1mbps) -28 db c/i -3rd acs c/i 3mhz (1mbps) -16 db c/i co co-channel c/i ( 250kbps) 9 db c/i +1st acs c/i 1mhz (250kbps) -13 db c/i -1st acs c/i 1mhz (250kbps) -16 db c/i +2nd acs c/i 2mhz (250kbps) -25 db c/i -2nd acs c/i 2mhz (250kbps) -9 db c/i +3rd acs c/i 3mhz (250kbps) -33 db c/i -3rd acs c/i 3mhz (250kbps) -33 db note: * device is esd sensitive. hbm (human body mode) is based on mil-std-883h method 3015.8. mm (machine mode) is based on jedec eia/jesd22-a115. function description state control state control diagram ? pin signal: vdd, ce ? spi register: pwr_up, prim_rx, en_aa, no_ ack, arc, ard ? system information: t ime out, ack received, ard elapsed, arc_cnt , tx fifo empty, ack packet transmitted, packet received BC9824 has built-in state machines that control the state transition between different modes. w hen a uto a cknowledge f eature i s d is abled , s tate transition will be fully controlled by mcu . power down mode in p ower d own m ode b c9824 i s i n sl eep m ode wi th minimal current consumption. spi interface is still ac - tive in this mode , and all register values are available by spi. power down mode is entered by setting the pwr_up bit in the config register to low. standby-i mode by setting the pwr_up bit in the config register to 1 and de-asserting ce to 0, the device enters standby-i mode. st andby-i m ode i s u sed t o m inimize a verage current c onsumption wh ile m aintaining sh ort st art- up time. in this mode, part of the crystal oscillator is a ctive. t his i s a lso t he m ode whi ch t he bc 9824 returns to from tx or rx mode when ce is set low.
rev. 1.00 5 october 20, 2015 BC9824 power down standby -i pwr _ up =1 start up time 1.5 ms pwr _ up =0 tx rx tx fifo not empty ce = 1 for more than 15us ard elapsed and arc _ cnt < arc tx setting 130us time out or ack received standby - ii tx fifo empty ce =1 tx fifo not empty ce =1 tx setting 130us tx finished ce =0 en _ aa =1 no _ ack =0 rx setting 130us vdd >1.9v ptx (prim_rx=0) state control diagram power down standby -i pwr _ up =1 start up time 1.5 ms pwr _ up =0 tx rx ce =0 ce =0 ack packet transmitted ce =1 rx setting 130us packet received en _ aa =1 no _ ack =0 tx setting 130us vdd >1.9v ce =1 rx setting 130us prx (prim_rx=1) state control diagram
rev. 1.00 6 october 20, 2015 BC9824 standby-ii mode in st andby-ii m ode m ore c lock buf fers a re a ctive than in standby-i mode and much more current is used. st andby-ii oc curs wh en ce i s he ld hi gh on a ptx d evice wi th e mpty t x fi fo. i f a n ew p acket is uploaded to the tx fifo in this mode, the device will automatically enter tx mode and the packet is transmitted. tx mode ? ptx device (prim_rx=0) the tx mode is an active mode where the ptx device transmits a packet. t o enter this mode from power down mode, the ptx device must have the pwr_up bit set high, prim_rx bit set low , a payload i n t he t x fifo , and a hi gh pu lse on t he ce for more than 10s. the ptx device stays in tx mode until it fnishes transmitting the current packet. if ce = 0 it returns to standby-i mode. if ce = 1, the next action is determined by t he st atus of t he t x fifo. if t he tx fifo is not empty the ptx device remains in tx m ode, t ransmitting t he ne xt pa cket. if t he t x fifo is empty the ptx device goes into standby-ii mode. it is import ant to never stay in tx mode for more than 4ms at one time. if t he a uto re transmit i s e nabled (e n_aa=1) a nd auto acknowledge is required (no_ack=0), the ptx devi ce wi ll ent er tx mode from st andby-i mode when ard elapsed and number of retried is less than arc. ? prx device (prim_rx=1) the pr x d evice wi ll e nter t x m ode f rom r x mode only when en_aa=1 and no_ack=0 in received pa cket t o t ransmit a cknowledge pa cket with pending payload in tx fifo. rx mode ? prx device (prim_rx=1) the rx m ode is a n a ctive mode where the BC9824 radio i s c onfigured t o b e a r eceiver. t o e nter t his mode from s tandby-i mode, the p rx device mus t have t he pw r_up b it se t h igh, pr im_rx b it se t high and the ce pin set high. or prx device can enter this mode from tx mode after transmitting an acknowledge packet when en_aa=1 and no_ ack=0 in received packet. in this mode the receiver demodulates the signals from t he r f c hannel, c onstantly p resenting t he demodulated data to the packet processing engine. the packet processing engine continuously searches for a va lid packet. if a val id pac ket is found ( by a m atching a ddress a nd a v alid c rc) the payload of the packet is presented in a vacant slot i n t he rx fifo. if t he rx fifo i s ful l, t he received packet is discarded. the prx device remains in rx mode until the mcu configures it to standby-i mode or power down mode. in rx mode a carrier detection (cd) signal is available. the cd is set to high when a rf signal is detecte d inside the receiving frequency channel. the internal cd signal is fltered before presented to c d r egister. t he r f si gnal m ust be pr esent fo r at least 128 s before the cd is set high. ? ptx device (prim_rx=0) the ptx device will enter rx mode from tx mode only when en_aa=1 and no_ack=0 to receive acknowledge packet .
rev. 1.00 7 october 20, 2015 BC9824 preamble 1 byte address 3~ 5 byte packet control 9/ 0 bit payload 0~ 32 byte crc 2/ 1 byte payload length 6 bit pid 2 bit no _ ack 1 bit packet format packet processing packet format the packet format has a preamble, address, packet control, payload and crc feld. ? preamble the preamble is a bit sequence used to detect 0 and 1 levels in the receiver . the preamble is one byte long and is either 01010101 or 10101010. if the first bit in the address is 1 the preamble is automatically set to 10101010 and if the frst bit is 0 t he pre amble i s a utomatically set t o 01010101. this is done to ensure there are enough transitions in the preamble to stabilize the receiver. ? address this is the address for the receiver . an address ensures that the packet is detected by the tar get receiver. the address feld can be confgured to be 3, 4, or 5 bytes long by the a w register. the prx device can open up to six data pipes to support up to six ptx devices with unique addresses. all six ptx device addresses are searched simultaneously . in prx side, the data pipes are enabled with the bits in the en_ rxaddr registe r. by default only data pipe 0 and 1 are enabled. each data pipe address is configured in the rx_ addr_px registers. each p ipe c an h ave u p t o 5 b ytes c onfigurable address. data pipe 0 has a unique 5 byte address. data pipes 1-5 share the 4 most signifcant address bytes. the lsb byte must be unique for all 6 pipes. to ensure that the ack packet from the prx is transmitted to the correct ptx, the prx takes the data pipe address where it received the packet and uses i t a s t he t x a ddress whe n t ransmitting t he ack packet. on t he prx , t he rx_addr_ pn, de fined a s t he pipe address, must be unique. on the ptx the tx_ addr must be the same as the rx_addr_p0 on the ptx, and as the pipe address for the designated pipe on the prx. no ot her da ta pi pe c an re ceive da ta unt il a c om - plete packet is received by a data pipe that has detected its address. when multiple ptx devices are transm itting to a prx, the ard can be used to sk ew t he a uto r etransmission so t hat t hey o nly block each other once. ? packet control when dynamic payload length function is enabled, t he pa cket c ontrol fi eld c ontains a 6 bi t payload length feld, a 2 bit pid (packet identity) feld and, a 1 bit no_ack fag. ? payload length the payload length field is only used if the dynamic payload length function is enabled. ? pid the 2 b it pi d fe ld i s u sed t o d etect wh ether t he received packet is new or retransmitted. pid prevents the prx device from presenting the same pa yload m ore t han onc e t o t he mcu. t he pid feld is incremented at the tx side for each new packet rece ived through the spi. the pid and crc fields are used by the prx device to determine whet her a pa cket i s ol d or ne w. w hen several da ta pa ckets a re l ost on t he l ink, t he pid felds may becom e equal to the last received pid. if a packet has the same pid as the previous packet, b c9824 c ompares t he c rc su ms f rom both packets. if the crc sums are also equal, the last received packet is considered a copy of the previously received packet and discarded. ? no_ack the no_ack fl ag i s only use d whe n t he a uto acknowledgement feature is used. setting the fag high, tell s the rece iver that the packet is not to be auto acknowledged. the ptx can set the no_ack flag bit in the packet control field with th e command: w_tx_ payload_noack . however, the function must frst be enabled in the fea ture register by setting the en_dyn_ack bit. w hen you use this option, the ptx goes directly to standby-i mode after trans mitting the packet and the p rx does not transmit an ack packet when it receives the packet.
rev. 1.00 8 october 20, 2015 BC9824 ? payload the payload is the user defined content of the packet. it can be 0 to 32 bytes w ide, and it is transmitted on-air as it is uploaded (unmodifed) to the device. the BC9824 provides two alternativ es for handling payload lengths, static and dynamic payload length. the static payload length of each of six data pipes can be individually set. the de fault a lternative i s st atic pa yload l ength. with st atic pa yload l ength a ll pa ckets be tween a transmitter and a receiver have the same length. static p ayload l ength i s se t b y t he r x_pw_px registers. the payload length on the transmitter side is set by the number of bytes clocked into the tx_fifo and must equal the val ue in the rx_ pw_px register on the receiver side. each pipe has its own payload length. dynamic payload length (dpl) is an alternative to static payload length. dpl enables the transmitter to send packets with variable payload length to the receiver. t his m eans for a syst em wi th di fferent payload lengths it is not necessary to scale the packet length to the longest payload. with dpl feature the BC9824 can decode the pay - load length of the received packet automatically instead of usi ng t he rx_pw _px re gisters. the mcu can read the length of the received payload by using the command : r_rx_pl_wid. in order to enable dp l the en _dpl bit in the feature register must be set. in rx mode the dynpd register has to be set. a ptx that transmits to a prx with dpl enabled must have the dpl_p0 bit in dynpd set. ? crc the cr c i s t he e rror de tection m echanism i n t he packet. the number of bytes in the crc is set by the crco bit in the config register . it may be either 1 or 2 bytes and is calculated over the address, packet control field, and payload. the polynomial for 1 byte crc is x 8 + x 2 + x + 1. initial value is 0xff . the polynomial for 2 byte crc is x 16 + x 12 + x 5 + 1. initial value is 0xffff . no packet is accepted by receive r side if the crc fails. packet handling BC9824 uses burst mode for payload transmission and receive. the t ransmitter f etches p ayload f rom t x fi fo, a u - tomatically assembles it into packet and transmits the packet in a very short burst period with 1mbps or 2mbps air data rate. after t ransmission, i f t he pt x p acket h as t he no_ ack fag set, BC9824 sets tx_ds and gives an active low interrupt irq to mcu . if the ptx is ack packet, the ptx needs receive ack from the prx and then asserts the tx_ds irq. the receiver automatically validates and disassembles received packet, if there is a valid packet within the new payload, it will write the payload into rx fifo, set rx_dr and give an active low interrupt irq to mcu. when auto acknowledge is enabled (en_aa=1), the ptx device will automatically wait for acknowledge packet after transmission, and re-transmit original packet with the delay of ard until a n acknowledge packet is received or the number of re-transmission exceeds a threshold arc. if the later one happens, BC9824 will set max_r t and give an active low in - terrupt irq to mcu. t wo packet loss counters ( arc_ cnt a nd pl os_cnt ) a re i ncremented e ach t ime a packet is lost. the arc_cnt counts the number of r etransmissions f or t he c urrent t ransaction. t he plos_cnt counts the total number of retransmis - sions since the last channel change. arc_cnt is reset by initiating a new transaction. plos_cnt is reset by wri ting t o t he rf_ch re gister. it i s possi ble to use t he i nformation i n t he obse rve_tx re gister to make an overall assessment of the channel quality. the ptx device will retransmit if its rx fifo is full but received ack frame has payload. as an alternative for ptx device to auto retransmit it is possible to manually set the BC9824 to retransmit a packet a number of times . this is done by the reuse_tx_pl command. when auto acknowledge is enabled, the prx device will a utomatically c heck t he no_ack fi eld i n re - ceived p acket, a nd i f no_ ack=0, i t wi ll a utomati - cally send a n acknowledge packet to ptx device. if en_ack_pay is set, and the acknowledge packet can also include pending payload in tx fifo.
rev. 1.00 9 october 20, 2015 BC9824 data and control interface tx/rx fifo the data fifo s are used to store payload that is to be transmitted (tx fifo) or payload that is received and ready to be clocke d out (rx fifo). the fifo is ac - cessible in both ptx mode and prx mode. there are three levels 32 bytes fifo for both tx and rx, s upporting both acknow ledge mode or no ac - knowledge mode with up to six pipes. ? tx three levels, 32 byte fifo ? rx three levels, 32 byte fifo both f ifo s have a controller and are acces sible through the spi by using dedicated spi commands. a tx fifo in prx can store payload for ack packets to three dif ferent ptx devi ces. if the tx fifo con - tains m ore t han one pa yload t o a pi pe, pa yloads a re handled using the frst in frst out principle. the tx fifo in a prx is blocked if all pending payloads are addressed t o pipe s where t he l ink t o t he pt x i s l ost. in this case, the mcu can fush the tx fifo by using the flush_tx command. the r x fifo i n prx m ay c ontain p ayload fr om up to three different ptx devices. a t x fi fo i n pt x c an h ave u p t o t hree p ayloads stored. the t x fi fo c an b e wr itten t o b y t hree c ommands, w_tx_payload and w_tx_p ayload_no_ ack in ptx mode and w_ack_p ayload in prx mode. al l t hree c ommands g ive a ccess t o t he t x_ pld register. the rx fifo can be read by the command r_rx_ payload in both ptx and prx mode. this com - mand gives access to the rx_pld register. the payload in tx fifo in a ptx is not removed if the max_rt irq is asserted. in the fifo_st atus register it is possible to read if the tx and rx fifo are full or empty . the tx_re - use bit is also available in the fifo_st atus regis - ter. tx_reuse is set by the spi command reuse_ tx_pl, and is reset by the spi command : w_tx_ payload or flush tx. interrupt in BC9824 there is an active low interrupt (irq) pin, which is activated when tx_ds irq, rx_dr irq or max_r t irq are set high by the state machine in the st atus register . the irq pin resets when mcu writes 1 to the irq source bit in the st atus regis - ter. the irq mask in the config register is used to select t he irq sourc es t hat a re a llowed t o a ssert t he irq pi n. by se tting one of t he mask bi ts hi gh, t he corresponding irq source is disabled. by default all irq sources are enabled. the 3 bit pipe information in the st atus register is updated during the irq pin high to low transition. if the st atus register is read during an irq pin high to low transition, the pipe information is unreliable. spi interface ? spi command the sp i commands are show n in the below table . every ne w c ommand m ust be st arted by a hi gh t o low transition on csn. in p arallel t o t he spi c ommand wo rd a pplied o n t he mosi p in, t he st atus r egister i s sh ifted se rially out on the miso pin. the serial shifting spi commands is in the follow - ing format: ? ? for all registers at bank 0 and register 9 to register 14 at bank 1 ? for register 0 to register 8 at bank 1
rev. 1.00 10 october 20, 2015 BC9824 command name command word (binary) # data bytes operation r_register 000a aaaa 1 to 5 lsb byte frst read command and status registers. aaaaa = 5 bit register map address w_register 001a aaaa 1 to 5 lsb byte frst write command and status registers. aaaaa = 5 bit register map address executable in power down or standby modes only. r_rx_payload 0110 0001 1 to 32 lsb byte frst read rx-payload: 1 C 32 bytes. a read operation always starts at byte 0. payload is deleted from fifo after it is read. used in rx mode. w_tx_payload 1010 0000 1 to 32 lsb byte frst write tx-payload: 1 C 32 bytes. a write operation always starts at byte 0 used in tx payload. flush_tx 1110 0001 0 flush tx fifo, used in tx mode flush_rx 1110 0010 0 flush rx fifo, used in rx mode should not be executed during transmission of acknowledge, that is, acknowledge package will not be completed. reuse_tx_pl 1110 0011 0 used for a ptx device reuse last transmitted payload. packets are repeatedly retransmitted as long as ce is high. tx payload reuse is active until w_tx_payload or flush tx is executed. tx payload reuse must not be activated or deactivated during package transmission activate 0101 0000 1 this write command followed by data 0x73 activates the following features: ? r_rx_pl_wid ? w_ack_payload ? w_tx_payload_noack a new activate command with the same data deactivates them again. this is executable in power down or stand by modes only. the r_rx_pl_wid, w_ack_payload, and w_tx_payload_noack features registers are initially in a deactivated state; a write has no effect, a read only results in zeros on miso. to activate these registers, use the activate command followed by data 0x73. then they can be accessed as any other register. use the same command and data to deactivate the registers again. this write command followed by data 0x53 toggles the register bank, and the current register bank number can be read out from reg7 [7] r_rx_pl_wid 0110 0000 read rx-payload width for the top r_rx_payload in the rx fifo. w_ack_ payload 1010 1ppp 1 to 32 lsb byte frst used in rx mode. write payload to be transmitted together with ack packet on pipe ppp. (ppp valid in the range from 000 to 101). maximum three ack packet payloads can be pending. payloads with same ppp are handled using frst in - frst out principle. write payload: 1C 32 bytes. a write operation always starts at byte 0. w_tx_payload_ no ack 1011 0000 1 to 32 lsb byte frst used in tx mode. disables autoack on this specifc packet. nop 1111 1111 0 no operation. might be used to read the status register spi command
rev. 1.00 11 october 20, 2015 BC9824 ? spi t iming x c7 c6 c5 c4 c3 c2 c1 c0 x d7 d6 d5 d4 d3 d2 d1 d0 x s7 s6 s5 s4 s3 s2 s1 s0 hi -z 0 0 0 0 0 0 0 0 hi -z x x s7 s6 s5 s4 s3 s2 s1 s0 d7 d6 d5 d4 d3 d2 d1 d0 sck csn mosi miso miso mosi write to spi register : read from spi register : c7 c6 c5 c4 c3 c2 c1 c0 x x spi timing cn: spi command bit sn: status register bit dn: data bit (lsb byte to msb byte, msb bit in each byte frst) note: the spi timing is for bank 0 and register 9 to 14 at bank 1. for register 0 to 8 at bank 1, the byte order is inversed that the msb byte is r/w before lsb byte. t csd csn sck c7 c6 c0 mosi s7 miso s0 t cc t ch t cl t dc t dh t cd t cdz t cwh t cch spi nop timing diagram symbol parameters min max units tdc data to sck setup 10 ns tdh sck to data hold 20 ns tcsd csn to data valid 38 ns tcd sck to data valid 55 ns tcl sck low time 40 ns tch sck high time 40 ns fsck sck frequency 0 8 mhz tr,tf sck rise and fall 100 ns tcc csn to sck setup 2 ns tcch sck to csn hold 2 ns tcwh csn inactive time 50 ns tcdz csn to output high z 38 ns spi timing parameter
rev. 1.00 12 october 20, 2015 BC9824 register map there are two register banks, which can be toggled by spi command activ ate followed with 0x53 byte, and bank stat us can be read from bank0_ reg7 [7]. register bank 0 address (hex) mnemonic bit reset value type description 00 config confguration register reserved 7 0 r/w only '0' allowed mask_rx_dr 6 0 r/w mask interrupt caused by rx_dr 1: interrupt not refected on the irq pin 0: refect rx_dr as active low interrupt on the irq pin mask_tx_ds 5 0 r/w mask interrupt caused by tx_ds 1: interrupt not refected on the irq pin 0: refect tx_ds as active low interrupt on the irq pin mask_max_rt 4 0 r/w mask interrupt caused by max_rt 1: interrupt not refected on the irq pin 0: refect max_rt as active low interrupt on the irq pin en_crc 3 1 r/w enable crc. forced high if one of the bits in the en_aa is high crco 2 0 r/w crc encoding scheme '0' - 1 byte '1' - 2 bytes pwr_up 1 0 r/w 1: power up, 0:power down prim_rx 0 0 r/w rx/tx control, 1: prx, 0: ptx 01 en_aa enable auto acknowledgment function reserved 7:6 00 r/w only '00' allowed enaa_p5 5 1 r/w enable auto acknowledgement data pipe 5 enaa_p4 4 1 r/w enable auto acknowledgement data pipe 4 enaa_p3 3 1 r/w enable auto acknowledgement data pipe 3 enaa_p2 2 1 r/w enable auto acknowledgement data pipe 2 enaa_p1 1 1 r/w enable auto acknowledgement data pipe 1 enaa_p0 0 1 r/w enable auto acknowledgement data pipe 0 02 en_rxaddr enabled rx addresses reserved 7:6 00 r/w only '00' allowed erx_p5 5 0 r/w enable data pipe 5. erx_p4 4 0 r/w enable data pipe 4. erx_p3 3 0 r/w enable data pipe 3. erx_p2 2 0 r/w enable data pipe 2. erx_p1 1 1 r/w enable data pipe 1. erx_p0 0 1 r/w enable data pipe 0. 03 setup_aw setup of address widths (common for all data pipes) reserved 7:2 000000 r/w only '000000' allowed aw 1:0 11 r/w rx/tx address feld width '00' - illegal '01' - 3 bytes '10' - 4 bytes '11' - 5 bytes lsb bytes are used if address width is below 5 bytes
rev. 1.00 13 october 20, 2015 BC9824 address (hex) mnemonic bit reset value type description 04 setup_retr setup of automatic retransmission ard 7:4 0000 r/w auto retransmi ssion delay 0000 C wait 250 u s 0001 C wait 500 u s 0010 C wait 750 u s .. 1111 C wait 4000 us (delay defned from end of transmission to start of next transmission) arc 3:0 0011 r/w auto retransmi ssion count 0000 Cre-transmit disabled 0001 C up to 1 re-transmi ssion on fail of aa 1111 C up to 15 re-transmi ssion on fail of aa 05 rf_ch rf channel reserved 7 0 r/w only '0' allowed rf_ch 6:0 0000010 r/w sets the frequency channel 06 rf_setup rf setup register reserved 7:6 0 r/w only '00' allowed rf_dr_low 5 0 r/w set air data rate. see rf_dr_high for encoding. pll_lock 4 0 r/w force pll lock signal. only used in test rf_dr_high 3 1 r/w set air data rate. encoding: rf_dr_low, rf_dr_high: 00 C 1mbps 0 1 C 2mbps (default) 10 C 250kbps 11 C 2mbps rf_pwr[1:0] 2:1 11 r/w set rf output power in tx mode rf_pwr[1:0] '00' C -26 dbm 01 C - 14 dbm 10 C -6 dbm 11 C -1 dbm lna_hcurr 0 1 r/w setup lna gain 0:low gain(20db down) 1:high gain 07 status status register (in parallel to the spi command word applied on the mosi pin, the status register is shifted serially out on the miso pin) rbank 7 0 r register bank selection states. switch register bank is done by spi command activate followed by 0x53 0: register bank 0 1: register bank 1 rx_dr 6 0 r/w data ready rx fifo interrupt asserted when new data arrives rx fifo write 1 to clear bit. max_rt 4 0 r/w maximum number of tx retransmits interrupt write 1 to clear bit. if max_rt is asserted it must be cleared to enable further communication. rx_p_no 3:1 111 r data pipe number for the payload available for reading from rx_fifo 000-101: data pipe number 110: not used 111: rx fifo empty tx_full 0 0 r tx fifo full fag. 1: tx fifo full 0: available locations in tx fifo
rev. 1.00 14 october 20, 2015 BC9824 address (hex) mnemonic bit reset value type description 08 observe_tx transmit observe register plos_cnt 7:4 0000 r count lost packets. the counter is overfow protected to 15, and discontinues at max until reset. the counter is reset by writing to rf_ch. arc_cnt 3:0 0000 r count retransmitted packets. the counter is reset when transmission of a new packet starts. 09 cd reserved 7:1 0000000 r cd 0 0 r carrier detect 0a rx_addr_p0 39:0 0xe7e7e 7e7e7 r/w receive address data pipe 0. 5 bytes maximum length. (lsb byte is written frst. write the number of bytes defned by setup_aw) 0b rx_addr_p1 39:0 0xc2c2c 2c2c2 r/w receive address data pipe 1. 5 bytes maximum length. (lsb byte is written frst. write the number of bytes defned by setup_aw) 0c rx_addr_p2 7:0 0xc3 r/w receive address data pipe 2. only lsb msb bytes is equal to rx_addr_p1[39:8] 0d rx_addr_p3 7:0 0xc4 r/w receive address data pipe 3. only lsb msb bytes is equal to rx_addr_p1[39:8] 0e rx_addr_p4 7:0 0xc5 r/w receive address data pipe 4. only lsb. msb bytes is equal to rx_addr_p1[39:8] 0f rx_addr_p5 7:0 0xc6 r/w receive address data pipe 5. only lsb. msb bytes is equal to rx_addr_p1[39:8] 10 tx_addr 39:0 0xe7e7e 7e7e7 r/w transmit address. used for a ptx device only. (lsb byte is written frst) set rx_addr_p0 equal to this address to handle automatic acknowledge if this is a ptx device 11 rx_pw_p0 reserved 7:6 00 r/w only '00' allowed rx_pw_p0 5:0 000000 r/w number of bytes in rx payload in data pipe 0 (1 to 32 bytes). 0: not used 1 = 1 byte 32 = 32 bytes 12 rx_pw_p1 reserved 7:6 00 r/w only '00' allowed rx_pw_p1 5:0 000000 r/w number of bytes in rx payload in data pipe 1 (1 to 32 bytes). 0: not used 1 = 1 byte 32 = 32 bytes 13 rx_pw_p2 reserved 7:6 00 r/w only '00' allowed rx_pw_p2 5:0 000000 r/w number of bytes in rx payload in data pipe 2 (1 to 32 bytes). 0: not used 1 = 1 byte 32 = 32 bytes
rev. 1.00 15 october 20, 2015 BC9824 address (hex) mnemonic bit reset value type description 14 rx_pw_p3 reserved 7:6 00 r/w only '00' allowed rx_pw_p3 5:0 000000 r/w number of bytes in rx payload in data pipe 3 (1 to 32 bytes). 0: not used 1 = 1 byte 32 = 32 bytes 15 rx_pw_p4 reserved 7:6 00 r/w only '00' allowed rx_pw_p4 5:0 000000 r/w number of bytes in rx payload in data pipe 4 (1 to 32 bytes). 0: not used 1 = 1 byte 32 = 32 bytes 16 rx_pw_p5 reserved 7:6 00 r/w only '00' allowed rx_pw_p5 5:0 000000 r/w number of bytes in rx payload in data pipe 5 (1 to 32 bytes). 0: not used 1 = 1 byte 32 = 32 bytes 17 fifo_status fifo status register reserved 7 0 r/w only '0' allowed tx_reuse 6 0 r reuse last transmitted data packet if set high. the packet is repeatedly retransmitted as long as ce is high. tx_reuse is set by the spi command reuse_tx_ pl, and is reset by the spi command w_tx_payload or flush tx tx_full 5 0 r tx fifo full fag 1: tx fifo full; 0: available locations in tx fifo tx_empty 4 0 r tx fifo empty fag. 1: tx fifo empty 0: data in tx fifo reserved 3:2 00 r/w only '00' allowed rx_full 1 0 r rx fifo full fag 1: rx fifo full 0: available locations in rx fifo rx_empty 0 1 r rx fifo empty fag 1: rx fifo empty 0: data in rx fifo
rev. 1.00 16 october 20, 2015 BC9824 address (hex) mnemonic bit reset value type description n/a ack_pld 255:0 x w written by separate spi command ack packet payload to data pipe number ppp given in spi command used in rx mode only maximum three ack packet payloads can be pending. payloads with same ppp are handled frst in frst out. n/a tx_pld 255:0 x w written by separate spi command tx data pay-load register 1 - 32 bytes. this register is implemented as a fifo with three levels. used in tx mode only n/a rx_pld 255:0 x r read by separate spi command rx data payload register. 1 - 32 bytes. this register is implemented as a fifo with three levels. all rx channels share the same fifo. 1c dynpd enable dynamic payload length reserved 7:6 0 r/w only 00 allowed dpl_p5 5 0 r/w enable dynamic payload length data pipe 5. (requires en_dpl and enaa_p5) dpl_p4 4 0 r/w enable dynamic payload length data pipe 4. (requires en_dpl and enaa_p4) dpl_p3 3 0 r/w enable dynamic payload length data pipe 3. (requires en_dpl and enaa_p3) dpl_p2 2 0 r/w enable dynamic payload length data pipe 2. (requires en_dpl and enaa_p2) dpl_p1 1 0 r/w enable dynamic payload length data pipe 1. (requires en_dpl and enaa_p1) dpl_p0 0 0 r/w enable dynamic payload length data pipe 0. (requires en_dpl and enaa_p0) 1d feature r/w feature register reserved 7:3 0 r/w only 00000 allowed en_dpl 2 0 r/w enables dynamic payload length en_ack_pay 1 0 r/w enables payload with ack en_dyn_ack 0 0 r/w enables the w_tx_payload_noack command note: dont write reserved registers and registers at other addresses in register bank 0
rev. 1.00 17 october 20, 2015 BC9824 register bank 1 address (hex) mnemonic bit reset value type description 00 31:0 0 w rite when normal mode. read received total bits when ber test mode. must write with 0x858ac01c 01 31:0 0 w rite when normal mode. read received error bits when ber test mode. must write with 0x 1103c960 02 31:0 0 w must write with 0x00000004 03 31:0 0x03001200 w must write with 0x000000 04 04 31:0 0 w for normal work mode: 1mbps,2mbps : 0x437d563f 250kbps : 0x437d663f for single carrier mode: low power : 0x437d563f normal power : 0x417d56 3f 05 31:0 0 w 250kbps :0x74106c9f 1mbps :0x14126c9f 2mbps :0x 74114c9f 06 31:0 0 w must write with 0x0007c022 07 6:0 31:8 0 w reserved rbank 7 0 r register bank selection states. switch register bank is done by spi command activate followed by 0x53 0: register bank 0 1: register bank 1 08 chip id 31:0 0 r store the chip id 09 0 r/w reserved 0a 0 r/w reserved 0b 0 r/w reserved 0c 31:0 0 r/w please initialize with 0x05731200 for 120us mode:0x00731200 0d 31:0 0 r/w please initialize with 0x0080b4 34 0e ramp 87:0 na r/w ramp curve please write with 0x cfffbdf3cf208082041041 note: dont write reserved registers and no defnition registers in register bank 1
rev. 1.00 18 october 20, 2015 BC9824 application circuit vss 33nf 3.3nh 10nh 2.7nh 20pf 20pf sck miso ce mosi 0r 1m csn irq vdd vss 2.4pf vss 4.7pf vss vss 1.8pf 1.8pf vss vss vss 16mhz nc vss vss 10uf vss 820nf vss vdd3if 6 vdd3rxrf 5 gnd 4 mosi 15 nc 10 rfn 3 vdd3b 8 cdvdd 7 gnd 17 sck 16 gnd 20 miso 14 csn 12 irq 13 xtalp 18 ce 11 gnd 9 xtaln 19 vddpa 1 rfp 2 BC9824 vss vss vss vss vss 0.1uf 0.1uf 10r 10r 10r vss 0.1uf vss vss 1 0 0 sma
rev. 1.00 19 october 20, 2015 BC9824 abbreviations ack acknowledgement arc auto retransmission count ard auto retransmi ssion delay cd c arrier detection ce chip enable crc cyclic redundancy check csn chip select not dpl dynamic payload length fifo first-in-first-out gfsk gaussian frequency shift keying ghz gigahertz lna low noise amplifer irq interrupt request ism industrial-scientifc-medical lsb least signifcant bit max_rt maximum retransmit mbps megabit per second mcu microcontroller unit mhz megahertz miso master in slave out mosi master o u t slave in msb most signifcant bit pa power amplifer pid packet identity bits pld payload prx primary rx ptx primary tx pwd_dwn power down pwd_up power up rf_ch radio frequency channel rssi received signal strength indicator rx receive rx_dr receive data ready sck spi clock spi serial peripheral interface tdd time division duplex tx transmit tx_ds transmit data sent xtal crystal
rev. 1.00 20 october 20, 2015 BC9824 package information note that the packag e information provided here is for consultation purposes o n ly. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to p ackaging is listed b elow. click o n th e relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information
rev. 1.00 21 october 20, 2015 BC9824 saw type 20-pin (4mm4mm) qfn outline dimensions symbol dimensions in inch min. nom. max. a 0.031 0.033 0.035 a1 0.000 0.001 0.002 a3 0.008 bsc b 0.007 0.010 0.012 d 0.157 bsc e 0.157 bsc e 0.020 bsc d2 0.075 0.079 0.081 e2 0.075 0.079 0.081 l 0.012 0.016 0.020 k 0.008 symbol dimensions in mm min. nom. max. a 0.800 0.850 0.900 a1 0.000 0.020 0.050 a3 0.203 bsc b 0.180 0.250 0.300 d 4.000 bsc e 4.000 bsc e 0.50 bsc d2 1.90 2.00 2.05 e2 1.90 2.00 2.05 l 0.30 0.40 0.50 k 0.20
rev. 1.00 22 october 20, 2015 BC9824 copyright ? 2015 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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